Pilot Integration of 3nm Semiconductor Technology
In line with industry needs, Moore’s law, IRDS’ (International Roadmap for Design and System – previously ITRS) white paper on technology roadmap, and ECSEL JU MASP 2018, the main objective of the PIn3S project is to discover, develop and demonstrate lithography, metrology, mask repair technology, devices and process modules enabling the micro-electronics industry to migrate to the 3nm node technology.
PIn3S is about “Pilot Integration of 3nm Semiconductor Technology”. By providing the industry integrated solutions for 3nm node; Device Manufacturing, Lithography- and Mask Repair Equipment it aims to pave the way towards the realization of the 3nm logic CMOS technology node. Whereas present available Extreme Ultra Violet (EUV) scanners have a Numerical Aperture (NA) of 0.33, to enable single exposure patterning at the 3nm node a new “Hyper NA” lithography system featuring an EUV scanner with an NA of 0.55 will be developed and demonstrated. This technology step towards Hyper NA is a solid step beyond the current state of the art and exceeds the impact of immersion technology for Deep Ultra Violet (DUV) lithography.
The project augments previous explorative work on the 3nm node by choosing solutions from the options explored and bringing them together in developing a 3nm node pilot integration flow targeting the demonstration of CMOS devices meeting the Power, Performance, Area and Cost (PPAC) requirements for the 3nm technology node. In that regard, process solutions selected for the final module and device integration will be subject of extensive process window studies aiming at improved process variability control. Extensive, high resolution, high precision, high throughput 2D and 3D metrology assessment is a corner stone of this process/module optimization. Dedicated work will be done to address and improve EUV photo resist performance with respect to line width control and stochastic variability. The latter is a prerequisite for the success of EUV in High Volume Manufacture. From a process technology and equipment perspective this work will be covered by imec in cooperation with AMBEL, IBS, RECIF, Coventor and Pfeiffer. From a Metrology perspective there will be the support of Applied Materials, Nova, KLA-Tencor, UPB-CSSNT (University POLITEHNICA of Bucharest) and Thermo Fisher.
In regard to Lithography, ASML will finalize the integration, testing and validation of the first ever Hyper NA EUV scanner system. Part of the work will be on Hyper NA anamorphic illuminator optics development covered by ZEISS SMT, supported by VDL ETG with the development of new high-tech structures in a that support and align precision components with high accuracy and stability in a vacuum environment. Additionally, there will be cooperation with Sioux CCM on the development of a particle free air bearing system in vacuum, Berliner Glas on new technology for the electrostatic clamp, Prodrive on wafer stage electronics, Reden on multi-physics modelling of particle-flow interactions and a new EUV sensor technology in cooperation with TU Delft and Fraunhofer IIS/EAS. The key final result will be to perform the first ever wafer exposures on a Hyper NA EUV tool.
To further enhance the control of the optical system the work will entail the development and implementation of a new deformable mirror technology by ZEISS SMT in cooperation with the University of Twente, Solmates, Fraunhofer FEP and scia Systems. The progress beyond the state of the art is to apply the forces on the mirrors in such a way that higher order aberrations will be corrected. By doing this, errors caused by time dependent effects like mirror heating will be reduced.
Moreover, ASML’s Deep UV immersion tool will be enhanced to enable mix and match of EUV and DUV scanner tools at the 3nm node level providing an integral lithography solution which is able to support the whole 3nm node process flow with a cost effective solution. ASML will work on wafer stage and advanced alignment models. Additionally, there will be cooperation between ZEISS SMT and ASML to integrate, test and qualify a first prototype DUV immersion projection optics with deformable mirror technology as well as between Berliner Glas and ASML on wafer table development.
The PIn3S project relates to the ECSEL JU work plan 2018 topic “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing. It addresses and targets, as set out in MASP, the major challenge of “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” by providing the equipment and process solutions for the 3nm node. Moreover, in regard to the device integration aspects of the project, also the major challenge of “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” is addressed. As such the project touches the core of the continuation of Moore’s law.
Over the past decades, the European semiconductor process and equipment sector has proven to be a solid innovation, employment and revenue growth engine.
The cost aware development process as proposed in the project will support the involved companies, and will place them in a more competitive position over their worldwide counterparts. Through their worldwide affiliations, the impact of the PIn3S project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to greatly benefit the European economy by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.
ECS Strategic Research Agenda focus areas:
ECSEL Call 2018
Start date: 10/2019
Duration: 36 months
Number of partners: 23
Number of countries: 6
Total investment: M€ 27